1. Field of the Invention
The present invention generally relates to a semiconductor memory device for performing a refresh operation and a refresh method thereof, and more specifically, to a technology of reducing self-refresh current and improving refresh characteristics by increasing sensing time only at a self-refresh mode.
2. Background of the Invention
In general, a semiconductor memory device to store data in a plurality of memory cells or to read the stored data comprises a plurality of bit lines, a plurality of word lines, circuits for selecting the bit lines or word lines and a plurality of sense amplifiers.
A DRAM of the memory devices comprises a selective transistor and a storage capacitor to improve integration density. However, since charges stored in the storage capacitor are leaked through the selective transistor in the DRAM, a periodical refresh operation is required to recharge the leakaged charges. This refresh operation is divided into an auto-refresh mode and a self-refresh mode.
FIG. 1 is a graph illustrating a row active operation of a conventional semiconductor memory device.
When data of the cell is at a high level, charges stored in the cell are shared in a bit line BL1 if a word line WL is activated. Thereafter, the bit line BL1 rises higher than a bit line bar /BL1 by a delta voltage dV1, the bit line BL1 is amplified to a core voltage VCORE level by a sense amplifier enable signal SAEN, and the bit line bar /BL1 is amplified to a ground voltage VSS level.
On the other hand, when data of the cell is at a low level, charges stored in the cell are shared in a bit line BL0 if a word line WL is activated. Thereafter, a bit line bar /BL0 falls lower than the bit line BL0 by a delta voltage dV0, the bit line bar /BL0 is amplified to the ground voltage VSS level by a sense amplifier, and the bit line BL0 is amplified to the core voltage VCORE level. Here, the delta voltages dV0 and dV1 are required to be higher than an off-set voltage of the sense amplifier.
However, when the sufficient delta voltages dV0 and dV1 are not secured in the operation of the semiconductor memory device, a sense amplifier enable signal is enabled in a state where the delta voltages dV0 and dV1 are lower than the off-set voltage of the sense amplifier. As a result, the sense amplifier cannot perform the precise data amplification operation.
In order to secure the sufficient delta voltages dV0 and dV1, sensing time to when the sense amplifier is driven from when the word line WL is enabled is required to be increased.
However, the sensing time is designed in consideration of the operating margin and the operating speed when the sufficient dV1 is obtained from the cell data. As a result, if the sensing time is increased both at the normal mode and at the refresh mode, the operating speed of the semiconductor memory device is reduced and power consumption is increased.